1/4 rev. b structure silicon monolithic integrated circuit product power management ls i for multimedia lsi on cellular type bh6174gul functions ? 2ch 600ma, high efficiency step-down converter. (16 steps adjustable vo by i 2 c) ? 5-ch 300ma, cmos-type ldos. power-save mode supported. (16 steps adjustable vo by i 2 c) ? ldo and step-down converter power on/off control enabled by i2c interface or external pin ? i 2 c compatible interface. (device address is ?1001111?) ? discharge resistance selectable for power-down sequence ramp speed control ? wafer level csp package(2.8mm 2.8mm) for space-constrained applications ? 0.5mm thin package to meet ultra-thin design requirements ? step-down converter output loop back available for ldo power supply (ldo3,4) absolute maximum ratings ta=25 ? c parameter symbol rating unit maximum supply voltage (vbat1,vbat2, pbat) vbatmax 6.0 v maximum supply voltage (pbat1, pbat2) vpbatmax 6.0 v maximum supply voltage (vin34) v34max 6.0 v maximum supply voltage (dvdd) vdvddmax 4.5 v maximum input voltage 1 ( lx1 , fb1 , lx2 , fb2 , out1 , out2 , out3 , out4 , out5 , vinmax1 vbat + 0.3 v maximum input voltage 2(nrst, clk, data) vinmax2 dvdd + 0.3 v power dissipation pd 960* 1 mw operating temperature range topr -35 +85 storage temperature range tstg -55 +125 *1 this is the allowable loss of when it is mounted on a rohm specification board 50mm 58mm. when a substrate is implemented, the allowable loss varies from the size and material of the substrate. to use at temperature higher than 25 ? c, derate 9.6mv per 1 ? c. recommended operating conditions (ta=25 ? c) parameter symbol range unit vbat1, 2 voltage vbat * 2 2.60 ~ 5.50 v pbat1, 2 voltage vpbat * 2 2.60 ~ 5.50 v vin34 voltage v34 * 3 1.70 ~ 5.50 v dvdd voltage vdvdd * 4 1.70 ~ 3.60 v *2 whenever the vbat or pbat or vin34 voltage is under the ldo or swreg output voltage, the ldo and swreg output is not guarante ed to meet its publis hed specifications. *3 vin34 power supply can be externally connected to the vbat and pbat power supply when necessary. *4 the dvdd voltage must be under the ba ttery voltage vbat, pbat at any times. * this product is not especially designed to be protected from radioactivity.
2/4 rev. b 3 25- 0.250.05 p=0.54 2 4 b c ( 0.15) index post s e 1 a a 0.05 p=0.54 2.80.05 b 0.55max b 2.80.05 0.40.05 5 s 0.06 a 1pin mark 0.10.05 0.40.05 d h6174 lot no. overview dimensions ball descriptions ball no. pin name b4 data c4 clk e4 vbat1 e1 vin34 a5 pbat1 a4 lx1 a3 pgnd1 b5 fb1 d4 nrst d5 out1 e5 out2 e2 out3 d1 out4 e3 out5 d2 refc c3 enall a1 pbat2 a2 lx2 b3 pgnd2 b1 fb2 c5 dvdd c1 gnd d3 test1 c2 test2 b2 vbat2 block diagram unit : mm vbat2 vbat1 swreg1 0.80-2.40v i2c if swreg2 0.80-2.40v ldo1 1.00-3.30v 5ma/300ma ldo2 1.00-3.30v 5ma/300ma ldo3 1.00-3.30v 5ma/300ma ldo4 1.00-3.30v 5ma/300ma ldo5 1.00-3.30v 5ma/300ma ref init 2.60 v init 3.00 v init 1.80 v 600ma init 1.01v 600ma init 1.00v init 1.00v 300ma 300ma 300ma 300ma 300ma init 3.30v out5 out4 out3 vin34 out2 out1 nrst data dvdd clk enall pbat1 lx1 pgnd1 fb1 pbat2 lx2 pgnd2 fb2 tsd refc test2 test1 gnd
3/4 rev. b electrical characteristics (unles s otherwise specified, ta=25 ? c, vbat1=vbat2=pbat=vin34=3.6v, dvdd=2.6v) parameter symbol min. ty p. max. unit condition circuit current vbat circuit current 1 (off) iqvb1 0.05 0.4 0.8 ? a ldo1~5=off, swreg1, 2=off, nrst=l, dvdd=0v vin34=vbat external connection vbat circuit current 2 (standby) iqvb2 0.1 0.7 1.4 ? a ldo1~5=off, swreg1, 2=off, nrst=h, dvdd=2.6v vin34=vbat external connection vbat circuit current 3 (active) iqvb3 110 220 330 ? a ldo1~5=on (no load , initial voltage) swreg1,2=on (no load initial voltage) nrst=h, dvdd=2.6v vin34=vbat external connection swreg1, 2 pwm/pfm auto mode dvdd quiescent current dvdd quiescent current 1 (off) iqvd1 - 0 1 ? a ldo1~5=off, swreg1, 2=off, nrst=l, dvdd=2.6v vin34=vbat external connection electrical characteristics (unles s otherwise specified, ta=25 ? c, vbat1=vbat2=pbat=vin34=3.6v, dvdd=2.6v) parameter symbol min. ty p. max. unit condition logic pin character nrst (cmos input) input ?h? level vih1 dvdd* 0.7 - dvdd+ 0.3 v pin voltage: dvdd input ?l? level vil1 -0.3 - dvdd* 0.3 v pin voltage: 0 v ?h? input current iic1 0 0.3 1 ? a pin voltage: 2.6v enall (nmos input) input ?h? level vih2 1.44 - vbat+ 0.3 v input ?l? level vil2 -0.3 - 0.4 v input leak current iic2 -1 0 1 ? a digital characteristics (digital pins: clk and data ) input "h" level vih3 dvdd* 0.7 - dvdd+ 0.3 v input "l" level vil3 -0.3 - dvdd* 0.3 v input leak current iic3 -1 0 1 ? a pin voltage: dvdd data output "l" level voltage vol 0 - 0.4 v iol=6ma swregs swreg1 output voltage vosw1i 0.9797 1.01 1.0403 v initial value, io=100ma , pwm mode swreg2 output voltage vosw 2i 0.970 1.00 1.030 v initial value, io=100ma , pwm mode ldos ldo1 output voltage vom1 0.97 1. 00 1.03 v initial value, io=5ma ldo2 output voltage vom2 2.522 2. 60 2.678 v initial value, io=5ma ldo3 output voltage vom3 2.91 3. 00 3.09 v initial value, io=5ma ldo4 output voltage vom4 1.764 1. 80 1.836 v initial value, io=5ma ldo5 output voltage vom5 3.201 3. 30 3.399 v initial value, io=5ma
4/4 rev. b use-related cautions (1) absolute maximum ratings if applied voltage (vbat1, vbat2, pbat1, pbat2, vin34, dvdd), operating te mperature range (toper), or other absolute maximum ra tings are exceeded, there is a risk of damage. since it is not possible to identify short, open , or other damage modes, if special modes in which absolute ma ximum ratings are exceeded are assumed, consider applying fuses or other physical safety measures. (2) recommended operating range this is the range within which it is possible to obtain roughl y the expected characteristics. for electrical characteristics, it is those that are guaranteed under the conditions for each parameter. ev en when these are within the recommended oper ating range, voltage and temperature characteris tics are indicated. (3) reverse connection of power supply connector there is a risk of damaging the lsi by reverse connection of the power supply connector. for protection from reverse connectio n, take measures such as externally placing a diode between the power supply and the power supply pin of the lsi. (4) power supply lines in the design of the board pattern, make power supply and gnd line wiring low impedance. when doing so, although the digital power supply and analog power supply are the same potential, separate the digital power sup ply pattern and analog power supply pattern to deter digital noise from enteri ng the analog power supply due to the common impedance of the wiring patterns. simil arly take pattern design into account for gnd lines as well. furthermore, for all power supply pins of the lsi, in conjunction with inserting capacitors between power supply and gnd pins, when using electrolytic capacitors, determine constants upon adequately confir ming that capacitance loss occurri ng at low temperatures is not a problem for various characteristics of the capacitors used. (5) gnd voltage make the potential of a gnd pin such that it will be the lowest potential even if operating below that. in addition, confirm t hat there are no pins for which the potential becomes less than a gnd by actually including transition phenomena. (6) shorts between pins and misinstallation when installing in the set board, pay adequate attention to orie ntation and placement discrepancies of the lsi. if it is insta lled erroneously, there is a risk of lsi damage. there also is a risk of damage if it is shorted by a foreign substance getting between pins or between a pin and a pow er supply or gnd. (7) operation in strong magnetic fields be careful when using the lsi in a strong magnetic field, since it may malfunction. (8) inspection in set board when inspecting the lsi in the se t board, since there is a risk of stress to the lsi when capacito rs are connected to low imped ance lsi pins, be sure to discharge for each process. moreover, when getting it on and off of a jig in the inspection process, always connect it after turning off the powe r supply, perform the inspection, and remove it after turning off the power supply. furthermore, as counterm easures against static electricity, use grounding in the assemb ly process and take appropriate care in transport and storage. (9) input pins parasitic elements inevitably are formed on an lsi structure due to potential relations hips. because parasitic elements operat e, they give rise to interference with circuit operation and may be the cause of malfunctions as well as damage. accordingly, take care not to apply a lower voltage than gnd to an input pin or use the lsi in other ways such that parasitic elements operate. moreover, do not appl y a voltage to an input pin when the power supply voltage is n ot being applied to the lsi. furthermore, when the power supp ly voltage is being applied, make each input pin a voltage less than the power supply voltage as well as wit hin the guaranteed values of electrical characteristics. (10) ground wiring pattern when there is a small signal gnd and a large current gnd, it is r ecommended that you separate the large current gnd pattern and small signal gnd pattern and provide single point grounding at the reference point of the set so that voltage variation due to resistance components of the pattern wiring and large currents do not cause the small signal gnd voltage to change. take care that the gnd wiring pattern of externally attached components also does not change. (11) externally attached capacitors when using ceramic capacitors for externally attached capacitors, determine constants up on taking into account a lowering of th e rated capacitance due to dc bias and capacitance change due to factors such as temperature. (12) thermal shutdown circuit (tsd) when the junction te mperature reaches the de fined value, the thermal shutdown circuit operates and turns the switch off. the t hermal shutdown circuit, which is aimed at isolating the lsi from thermal runaway as much as possibl e, is not aimed at the protection or guarantee of the lsi. t herefore, do not continuously use the lsi with this circuit operating or use the lsi assuming its operation. (13) thermal design perform thermal design in which there are ad equate margins by taking into account the permissible dissipation (pd) in actual st ates of use. (14) rush current extra care must be taken on power coupling, power, ground line impedance, and pcb design while excess amount of rush current mi ght instantly flow through the power line when powering-up a lsi which is equipped with several power supplies, depending on on/off sequence, and ramp delays.
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